In an effort to increase device densities and reduce critical dimensions (CDs) in semiconductor devices, traditional gate structures are replaced with gates having high-k dielectrics and metal electrodes. High-k dielectrics can provide enhanced capacitance in comparison to an equivalent thickness of silicon oxide. A metal electrode with a specified work function can avoid charge carrier depletion proximate to the electrode interface with the high-k dielectric. However, the electrodes for p-channel and n-channel transistors may require different metals to provide specified work functions.
Some metals for gate electrodes can be adversely affected by processing used to form source and drain regions; particularly, annealing to repair source and drain implant damage can shift the work function of electrode metals. This has led to various new manufacturing processes, including replacement gate (gate-last) processes. In a replacement gate process, a gate stack is formed with polysilicon in place of the electrode metal. After source and drain regions are formed and annealed, the polysilicon is removed to form trenches which are then filled with the desired electrode metals.
It is difficult to adequately fill the trenches as gate size decreases. In addition to small feature size, the gaps created by dummy gate removal during the gate last process often have different profiles at different portions of a transistor array, due to localized etching effects. Gaps at an edge of a transistor array and gaps toward a center of the transistor array can have different profiles (for example, re-entrant and vertical, respectively) and therefore different process requirements to fill adequately. Tuning the process to fill adequately for different profiles is difficult.
Attempts at improving the gate fill includes forming a tapered dummy gate such that the worst edge profile after dummy gate removal is vertical, instead of re-entrant. However, a tapered dummy gate shadows the self-aligned implantation processes and form varying doped regions in a transistor array. Further, formation of a tapered dummy gate involves hard-to-control re-entrant etching of polysilicon. Thus, improvements in gate-fill in a gate last process continue to be sought.